1. Technical Field
The inventive concept relates to a semiconductor memory device, and more particularly, to a semiconductor memory device in which a method of controlling a bit line sense amplifier that senses and amplifies data stored in a memory cell is improved.
2. Discussion of Related Art
Semiconductor memory devices (e.g., dynamic random access memories (DRAMs)) are generally arranged in an array of memory cells. Each column of the array is composed of a bit line and a complementary bit line (hereinafter referred to as a bit line pair) with each bit line connected to every other memory cell in the column, for example. To read data stored in a memory cell, a small voltage difference generated between a bit line pair, which is caused by a charge shared between the bit line receiving the data and a capacitor of the memory cell, is sensed and amplified to produce a binary logic signal. A bit line sense amplifier is used for sensing and amplifying the small voltage difference generated between the bit line pair. The bit line sense amplifier also writes back the data read from the memory cell.
Bit line sense amplifiers affect both memory access time and overall power dissipation. Bit line leakage current, however, can adversely affect the bit line sense amplifier sensing speed during read operations. Accordingly, there exists a need to reduce bit line leakage current.